hanen chenini

Doctor in electronics and systems

Present–Nov.24
Firmware engineer, Quantized Technologies Inc., Calgary, Canada.
Project : FPGA control of next-generation quantum key distribution solution.

Oct.2024–Feb.2022
Postdoctoral researcher, Quantum Cloud Lab, Calgary, Canada.
Topic : The design and implementation of FPGA based control system for MDI-QKD
prototype.

Jan.2022–June 2021
Visitor Professor, Radio Lab, Calgary, Canada.
Project : Adaptive Digital Predistortion for RF Power Amplifier Linearization.
 

May.2021–Sept.2019
Postdoctoral researcher, Microwave Electronics Research Laboratory,
Tunis, Tunisia.
Topic : The design and implementation of an adaptive Digital Predistorter DPD for RF
Power Amplifier (PA) suitable for the linearization of narrowband and wideband transmitters
developed with a hybrid FPGA platform.
Collaborations: This work is supported by iRadio Laboratory, Schulich School of Engineering,
University of Calgary, Calgary, Canada.

Aug.2019–
July 2018
Electronic engineer, Centre for Research on Microelectronics and
Nanotechnology, Sousse, Tunisia.
Topic : This work aims to propose hardware reconfigurable architectures for implementing
real time DPD applications with stringent resource-consumption and runtime constraints.
The proposed adaptive DPD algorithm is carefully performed, in order to meet the real time
execution requirements, in the Zynq-7000 Field Programmable Gate Array (FPGA) with an
Analog Devices AD9371 Wideband Transceiver.
Collaborations: This work is supported by iRadio Laboratory, Schulich School of Engineering,
University of Calgary, Calgary, Canada.
 

June2018- Sept.2015
Assistant Professeur, Higher Institute of Industrial Systems of Gabes
ISSIG, Gabes, Tunisia.
Department of Electrical and Electronic Engineering.

June2015-June.2014
Postdoctoral researcher, Lab-STICC, UMR 6285, University of Western
Brittany, Brest, France.
Topic : Unmanned Aerial Vehicle (UAV) with embedded intelligence, which divided into
three themes of Human-Machine Interactions, Trajectories / Path Planning, and Embedded
Systems, using Reconfigurable FPGA Architecture, to be dynamically configured according
to UAV mission requirements.
Collaborations: This work is supported by SWARMS, a three year collaborative project
between LabSTICC, a CNRS / Telecom Bretagne / UBO Univ. / UBS Univ. Lab. in
Brest and Lorient in France, and the Australian Research Centre for Aerospace Automation
(ARCAA), Queensland University of Technology QUT in Brisbane, Australia.

May2014- Jan2011
PhD Student Researcher, Pascal Institute, UMR 6602, Blaise Pascal
University, Clermont-Ferrand, France.
Topic : This work aims to propose a new design methodology which offers more
opportunities for accelerating the parallelization of sequential processing image algorithms
on parallel and pipeline architecture. The proposed approach provides a rapid prototyping
tool as a graphic programming environment (CubeGen). Further, it offers a set of parallel
software skeletons as a communication library, providing a software abstraction to enable
quick implementation of complex image processing applications on field-programmable
gate array (FPGA) platform. The goals then are to quantify the impact of taking several
complex applications in the developed MPSoC approach and therefore to demonstrate
the validity of our original approach. This allows enhancing our libraries (hardware IPs or
parallel skeletons).
Collaborations : This work has been conducted in the context of an european euripides
project SEAMOVES.

July 2008 : Engineering degree in Industrial Electronic, National Engineering School of
Sousse ENISO, Sousse University, Tunisia.
Oct. 2009 :  M.S. in Embedded Systems, ENISO, Sousse University, Tunisia, Thesis : Implementation of image processing application on homogeneous MPSoC architecture
based softcore processors.
May. 2014: Ph.D. in electronics and systems, Pascal Institute, UMR 6602, Blaise Pascal
University, Clermont-Ferrand, France, Thesis: A Rapid design methodology for
generating of parallel image processing applications and parallel architectures for
smart camera.