Sr Staff Engineer, SoC RTL Design - Toronto - Tenstorrent

    Tenstorrent
    Tenstorrent Toronto

    3 days ago

    Description

    Overview

    Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

    Responsibilities

    • Design and develop the Fabric and Memory subsystems from scratch for a high-performance CPU, working closely with the DV, physical design, and architecture teams.
    • Create RTL implementations in Verilog using both industry-standard tools and open-source infrastructure.
    • Collaborate with cross-functional teams, including design, test, and post-silicon validation, to ensure seamless delivery of the Fabric and Memory subsystems.
    • Evaluate and integrate 3rd-party IP components into the subsystem to meet performance and design goals.
    • Optimize power, performance, and area (PPA) by working closely with performance modeling, DV, and physical design engineers to make informed trade-offs.
    • Conduct experiments with RTL and analyze synthesis, timing, and power results to improve design quality.
    • Debug complex RTL/logic issues across different design hierarchies (core, chip) in both pre-silicon and post-silicon environments.
    • Enhance RTL design infrastructure and tools to streamline development and ensure consistency across projects.

    Experience & Qualifications

    • BS/MS/PhD in EE/ECE/CE/CS with at, with 5+ years of experience in Fabric or Memory subsystem design.
    • Extensive experience with CPU and GPU fabrics, including cache coherence protocols and memory ordering models (e.g., MOESI).
    • Strong understanding of interconnect topologies and protocols such as CHI, AXI, ACE, TileLink. Die-to-die, Ethernet, and I/O protocols are also relevant
    • Proven ability to tightly couple memory subsystems with CPU cores, optimizing data paths, bandwidth, and latency to meet system requirements.
    • Experience evaluating PPA trade-offs and working with synthesis, timing, and power tools to meet stringent design targets.
    • Hands-on experience with hardware description languages (Verilog, SystemVerilog) and simulators like VCS, NC, and Verilator.
    • Expertise in microarchitecture definition and specification development for complex memory systems.
    • Strong debugging and problem-solving skills across hierarchical levels (core, fabric, and chip) in both pre- and post-silicon environments.

    Benefits

    Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

    Compliance

    Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.

    As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment.

    If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.


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