AMD India Pvt Ltd

Design/Design Verification Engineer for IP Deployment (BB-3FF55)

Found in: Neuvoo Bulk CA

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. Design/Design Verification Engineer for IP Deployment Role The Display IP is one of the foundational IP's within AMD and is incorporated in all AMD SOC's which feature direct connectivity to a display device through Display Port, HDMI or USB-C connectors. Beyond the output encoding, the Display IP plays a significant role in the pixel processing and system power reduction strategies within the SOC. As a member of the IP team, the candidate would be responsible for identifying and executing sustainable technical solutions to enable integration of the Display IP design and DV collateral into AMD SOC environments. This position would require the individual to draw upon proven industry design and/or design verification experiences to ensure successful program execution. The Display Architecture, Design and DV team is based in Markham, Canada(just North of Toronto) and interacts daily with the Major Design centers across the globe. . Person The Display Controller team within the Radeon Technologies Group(RTG) is looking for an individual to participate in the Display IP deployment into various SOCs within AMD. Education and Experience Requirements Minimum of 7 years of proven design and verification experience on large ASIC development projects Very strong background in Verilog, System Verilog, C/C /OOO coding techniques Experience working with Cadence NCSIM, Synopsys VCS or equivalent Experience working with UVM, OVM or equivalent Experience with scripting languages, Ruby/Python/Tcl/BASH/etc. Strong analytical skills and attention to detail Excellent written and communication skills Experience with display/display related technologies Understanding of the IP integration and interactions within an SOC Deep understanding of computer architecture Must be a self-starter and able to independently drive tasks to completion. Demonstrates the ability to debug issues and quickly identify viable solutions Team player with proven leadership skills Responsibilities Understand the functional and performance requirements of the Display IP within an APU and dGPU SOC Scope requirements and resources to meet project schedules Compose test and coverage plan to ensure functional completeness in an SOC environment Work with SOC teams to debug test environment issues and failing test cases. Provide hands on leadership of a small team of Engineers as required to meet program development goals Provide guidance and/or act as a liaison between IP and SOC design teams for synthesis and physical layout issues Codeline management Signoff IP quality for delivery into SOC Effectively communicate with multi-disciplined teams located across the globe Gather, attend and present technical status on a weekly basis Academic Cridentials Min. Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering.

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