Description:

Develop Verilog test cases for the verification of a mixed signal ASIC for an optical modem Provide debug assistance for the ASIC design Write scripts to automate some tasks of the ASIC design and verification process Create scripts and run validation test in the lab Education & Experience Necessary For Success Strong programming experience in C, Verilog and/or SystemVerilog Solid knowledge of digital circuit design and verification Working knowledge of DSP and communication theories Experience with Matlab and tcl will be an asset Great communication skills and team work. MS candidate or senior BS student in Electrical or Computer Engineering