Senior AI/ML ASIC Design Verification - Markham - Qualcomm

Description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

QUALCOMM is the world's leading developer of next‑generation wireless and multimedia technology.

We are seeking an ASIC Design Verification engineer to help build world‑class AI/ML hardware IP for upcoming compute and multimedia products. The ideal candidate has experience in formal verification (FPV/DPV) or assertion‑based verification, but strong candidates with functional verification background (UVM/SystemVerilog) and an interest in growing their skills in formal methodology are also encouraged to apply. This role offers an excellent opportunity to contribute to cutting‑edge ML hardware while developing expertise across both formal and simulation‑based verification flo

As a member of the team,  your responsibilities include:

• Collaborate closely with RTL design, architecture, and verification leads to develop block‑level verification strategies and formal test plans for AI/ML/DSP IP.
• Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and industry‑standard formal tools (e.g.  VC Formal).
• Write assertions, cover properties, and interface checkers to validate protocol correctness, control logic behavior, and corner‑case scenarios.
• Apply sound ASIC engineering practices to debug architecture, design, or verification issues with minimal supervision, using counterexamples, bounded proofs, abstractions, and formal constraints.
• Collaborate with the simulation DV team to ensure alignment between formal‑based and UVM‑based verification approaches.
• Develop or integrate reference models (C/SystemC/Python)
• Analyze formal coverage, assertion coverage, and unreachable code, and drive convergence through model refinement or abstraction techniques.
• Participate in the overall verification flow, including RTL code coverage, functional coverage analysis, and (when appropriate) gate‑level checks.
• Identify opportunities for productivity improvements, including reusable property templates, automated scripts, better debug flows, or enhancements to verification methodology.
• Communicate promptly and clearly with the verification lead regarding risks, blockers, or deviations from the planned schedule or verification goals.

Required Competencies:

• Strong understanding of digital design fundamentals, including combinational/sequential logic, finite state machines, datapaths, and control logic.
• Hands‑on experience with SystemVerilog Assertions (SVA) for protocol checking, control logic validation, and coverage.
• Experience using at least one formal verification tool, such as Synopsys VC Formal, Cadence JasperGold, or Siemens Questa Formal.
• Hands‑on experience in functional verification using SystemVerilog, UVM, or similar methodology.
• Experience with reference models implementation or integration.
• Proficiency with scripting languages such as Python, Perl, Tcl, or shell for automation, debug acceleration, or flow improvements.
• Strong analytical/problem‑solving skills and willingness to learn new verification techniques.
• Effective communication skills for interacting with RTL designers, architects, and DV leads to clarify requirements and verification intent.
• Ability to document test plans, assumptions, assertions, and verification results clearly and concisely.
• Self‑motivated and able to take ownership of verification tasks with minimal supervision.

Preferred Qualifications

• Experience verifying AI/ML, DSP, or compute hardware.
• Knowledge of formal methodologies such as abstraction techniques, induction, convergence strategies, or cut‑point modeling.
• Experience with Formal Datapath Verification (DPV) on complex arithmetic or ML datapaths.
• Experience with RTL coding in Verilog/SystemVerilog.
• Strong curiosity and interest in advancing verification methodology, tooling, or automation.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability- or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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Pay range and Other Compensation & Benefits:

$104, $154,900.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.

If you would like more information about this role, please contact Qualcomm Careers.