Senior Design Verification Engineer - Toronto - Talentlab

    Talentlab
    Talentlab Toronto

    1 day ago

    Description

    Senior Design Verification Engineer

    Our client is a key player in advancing digital technology by accelerating high-performance data communication—from AI and the metaverse to seamless video and beyond. Their technology is foundational to innovation across data-heavy industries such as data centers, AI, networking, storage, 5G, and autonomous vehicles. Known for their cutting-edge solutions and reliable execution, they help shape the future of digital systems.

    The Digital Design Verification team fosters a collaborative, growth-oriented culture where engineers are encouraged to take on new challenges, learn continuously, and contribute to impactful projects. This group is dynamic, supportive, and a great fit for professionals looking to build their career in semiconductors.

    What You'll Do

    • Review design specifications and develop robust verification plans.

    • Build testbenches, run simulations, and debug failures to uncover design bugs.

    • Take initiative in leading, planning, and coordinating verification tasks with team members.

    • Create behavioral models of analog circuits.

    • Support bit-matching between RTL designs and MATLAB system models.

    • Integrate third-party VIPs for compliance testing of standard protocols.

    • Prepare design IP releases for customer delivery.

    • Collaborate in post-silicon validation and bring-up efforts.

    • Work closely with cross-functional teams—including Design, Systems, Analog, Firmware, and PD—to ensure final verification closure.

    • Continuously improve verification methodologies, tools, and team processes.

    What You'll Need

    • 3 to 8 years of relevant experience in design verification.

    • Strong skills in SystemVerilog and UVM for constrained-random verification.

    • Experience verifying SerDes PHYs, DSPs, and mixed-signal analog designs.

    • Knowledge of Ethernet and PCIe protocols is highly desirable.

    • Familiarity with formal verification and power-aware UPF verification techniques.

    • Proficiency in SystemVerilog, UVM, Python, Perl, C/C++, and GNU Make.

    Please reach out to with your resume if you're a fit for the position and interested in learning more.

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