Mixed Signal Engineering Intern - Ottawa, Ontario

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We're a technology company that leads with our ...

Job description

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We're a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

Why Ciena?

• We're a company rooted in people—seeking to create a vibrant and inclusive environment, where everyone feels they can belong.
• Accelerate your career path by gaining hands-on experience and exposure to the latest technology. Our interns and graduates work on real projects in real time in world class labs. Be a part of tomorrow's future – today.
• Mentoring. Networking. Leadership Opportunities. We recognize that the learning doesn't stop when you leave school - we champion a team environment for development and provide the tools to achieve success.
• We are big proponents of life-work integration. Our people make a big difference at Ciena, but we want to shine light on their differences outside of working hours too. CienaCares supports non-profit causes important to employees by matching employee financial contributions and dedicating time for volunteering.

How You Will Contribute
You will be part of an industry-leading multidisciplinary organization that develops high-baud-rate modems for next-generation optical communication networks. The specific team to which you will report specializes in the design and integration of custom mixed-signal macros into a 'Big Digital Little Analog' ASIC design flow. We perform this work using the most advanced nanoscale CMOS technologies, enabling the industry's highest baud rate and lowest power optical and electrical interfaces. You will also be deeply involved in designing custom mixed-signal circuits clocked at frequencies of 10 GHz and above. This necessitates that you be highly proficient in layout-driven design flows and schematic capture and that you be an expert in custom digital design principles and practice.

• The position will utilize all your acquired skills in electronics, digital systems, VLSI design, and computer-aided design tools. Your success will depend heavily on your ability to independently solve challenging engineering design problems. Attention to detail
• You will gain experience creating functional descriptions of digital designs at both the register transfer level and through schematic capture with standard cells.
• During your internship, you will learn to generate representations of the mixed signal blocks, including Verilog, Library Exchange Format, Liberty timing files, documentation, preliminary and final layout files, and spice netlists for chip-level LVS.

What Does Ciena Expect of You?

• A sense of urgency – what's important to the customer is equally important to you. You make getting things done a priority.
• Integrity – you hold yourself to the highest level of personal and professional standards of conduct.
• A commitment to innovation – you continually seek to learn, understand new technologies and ever-changing market conditions, and endeavor to apply that knowledge to Ciena's advantage.
• You embrace change – thriving in a diverse environment of ever-changing priorities and sometimes stressful situations.
• The flexibility to work independently with minimal supervision as well as part of a broader team.

The Must Haves

• Making progress toward earning a bachelor's degree in computer or electrical engineering.
• An awareness and comprehension of laboratory test procedures, electronics, and numerical methodologies.
• Integrated circuit computer-aided design, including parasitic extraction, layout, design rule checking, layout versus schematic verification, and SPICE circuit simulation.
• Strong programming skills with a track record of accomplishment in Verilog, C++, and Python.
• Experience with Synopsis Integrated Circuit Compiler II or Cadence Innovus would be major assets.
• Strict self-discipline, attention to detail, and the drive to produce work of the highest caliber.

Assets

• Excellent oral and written communication skills
• Confident working in both Windows and Linux environments

Pay Range
The hourly pay range for this position is $ $34.00

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.

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At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.