praveen prakash

Holding Canadian Open work Visa. An experienced FPGA design engineer with expertise in both hardware and RTL design, RTL simulation and debugging. Good in performing timely deliveries. Willingness to venture new arenas and take up challenges.

SENIOR SOFTWARE ENGINEER FPGA DESIGN, Analog Devices (Deputed from LeadSoC), Bangalore M AY 2 0 2 2 • 

Following Agile/scrum method of project management. • Experience in using Jira for project management. • Register Transfer Level RTL logic design using Verilog and System Verilog. • Well-versed with vivado tool and associate IP’s. • Experience with complete FPGA flows involving synthesize, simulation, timing closure. • Experience in git bitbucket. • Knowledge on basics of scripts. • Experience in using ETX Environment 

SENIOR SOFTWARE ENGINEER FPGA DESIGN, Quest Global, Trivandrum J U LY 2 0 2 1 — A P R I L 2 0 2 2

 • Register Transfer Level RTL logic design using VHDL/Verilog. • Experience industrial ethernet protocol like Powerlink enhanced ethernet MAC. • Experience in Synthesis / Understanding of timing concepts in Altera FPGA Implementation • Hands-on experience with integration issues like clocking, reset, memory map, hierarchical bus interconnect. • Hands on experience with switch IP integration. • Experience in GOWIN FPGA. 

FPGA Hardware Design Engineer, Mistral Solutions, Bangalore M AY 2 0 1 9 — J U LY 2 0 2 1

 • Register Transfer Level RTL logic design using VHDL/Verilog. • Experience with design verification, synthesis, timing/power analysis. • Experience in Synthesis / Understanding of timing concepts in Xilinx FPGA. Implementation • Experience in communication SPI, IIC, AXI protocols. • Hands-on experience with integration issues like clocking, reset, memory map, hierarchical bus interconnect. • Experience in Effective way of IP instantiation. • Experience in Hardware design. • Experience in LATTICE and Xilinx FPGA. 

Design verification (SoC) intern, Sion Semiconductor, Bangalore D E C E M B E R 2 0 1 8 — A P R I L 2 0 1 9 

• RTL design and Functional verification (RTL) using HDL• Develop verification environment and testbench components such as BFMs and checkers. • Develop verification environment and test bench components in System Verilog. 

Engineer Trainee, CENTER FOR DEVELOPMENT OF ADVANCED COMPUTING, Trivandrum S E P T E M B E R 2 0 1 4 — A U G U S T 2 0 1 5 

• Embedded C programming for PIC Microcontrollers Peripherals Such as SPI, UART, I2C protocols. • FPGA Programming in Xilinx ISE. • Circuit Designing Using Orcad. • Circuit Debugging, faults identification and rectification. • Assembly and testing of analogue and Digital PCBs.

Master Of Technology, Electronics (Signal processing) , Govt. Engineering College, Barton Hill, Trivandrum