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    Physical Design Engineer - Vancouver, Canada - AMD

    AMD
    AMD Vancouver, Canada

    3 weeks ago

    AMD background
    Full time
    Description

    Job Description

    WHAT YOU DO AT AMD CHANGES EVERYTHING

    We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

    AMD together we advance_

    THE ROLE:

    This is a Physical Design Engineering role that will require to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification

    THE PERSON:

    Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams

    KEY RESPONSIBILTIES:

    This engineer will work on high-speed multi-gigabit SerDes PHY designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. You will also support floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

    PREFERRED EXPERIENCE:

  • Working experience in high speed multi-gigabit SerDes PHY designs or other high performance IP designs
  • Proficiency in Python and/or Perl is required. Additional languages are a plus.
  • Versatility with scripts to automate design flow, and quality checks.
  • Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications.
  • Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
  • Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications
  • Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
  • Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
  • Strong scripting skills in multiple languages (Shell and Tcl are a must, Perl and Python are good to know)
  • Familiar with flow development including creating a good user interface, testing/improving run-time, debugging issues
  • Knowledge of EDA tools such as Genus, Innovus, Quantus, Tempus, Joules, Virtuoso, Nanotime, Spice and preferably how they work under the hood
  • Strong technical background in VLSI, ASIC, and EDA fundamentals
  • Background in physical or custom design is a plus
  • Self-starter with passion for growth, ability to quickly learn, enthusiasm for continuous learning and sharing findings across the team
  • Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated
  • Ability to work well in a team, multi-task, and be productive under aggressive schedules
  • Able to demonstrate the fundamentals of IP analysis - timing, noise, physical verification, electrical analysis
  • Working knowledge of IP collateral delivered by design teams such as Liberty, UPF, LEF, GDS or Verilog
  • Proficiency in Python and/or Perl is required. Additional languages are a plus.
  • Working knowledge of software unit test and regression
  • Working knowledge of version control software like GIT or Perforce
  • Working knowledge of Unix and Shell scripting
  • Working knowledge of job scheduling systems in a high performance compute environment
  • Experience with testing IP collateral is a plus
  • Familiarity with EDA tools used to analyze and QA IP is a plus
  • Familiarity with dependency aware flow control tools is a plus

    ACADEMIC CREDENTIALS:

  • Major in EE, CS or related, Bachelors

    LOCATION:

  • Vancouver, BC

    #LI-TB2

    Benefits offered are described: AMD benefits at a glance.

    AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

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