- Prime the verification activities for a block or an entire chip.
- Develop verification environment architecture using UVM.
- Document test environment associations and write test cases.
- Employ constrained random verification approaches when possible.
- Support lab bring-up with direct test cases.
- Perform code and functional coverage.
- 10+ years of experience in ASIC verification.
- Highly skilled in Verilog, SystemVerilog, other hardware description languages, and scripting languages.
- Significant experience with OVM/UVM methodologies.
- Familiarity with constrained random verification techniques, assertions and functional coverage.
- Experience with SONET, OTN, Ethernet, PCIe is a significant asset.
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Senior ASIC Verification Engineer - Ottawa, Canada - European Recruitment
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Description
Senior ASIC Verification Engineer
A Semiconductor design company are looking for an experienced ASIC Verification Engineer to join their team, to work on cutting-edge projects across various products.
Due to stable and organic growth as a result of having a strong reputation in the industry, the business is going from strength to strength and is keen to build on its current design expertise.
Overview:
Join the team as a Senior ASIC Verification Engineer and contribute to the success of cutting-edge ASIC projects at advanced technology nodes, reaching down to 3nm FinFET. As a crucial member of our dynamic and highly skilled team, you will play a pivotal role in ensuring the functional integrity of complex System-on-Chips (SOCs). Leverage your expertise in SystemVerilog, UVM, and scripting languages to drive prime verification activities and employ state-of-the-art methodologies and tools to validate designs.
Key Responsibilities:
Key Qualifications:
Interested? Apply directly through LinkedIn, or send your CV to
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