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    System-on-Chip Design Engineer - British Columbia, Canada - eTeam

    eTeam
    eTeam British Columbia, Canada

    4 days ago

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    Human Resources
    Description

    Job Title: SoC Design Engineer/ SoC Verification Engineer

    Location: Vancouver, BC V6P 6N6

    Duration: 12+ Months

    Pay Rate: CAD $60/hr on T4 (All inclusive)

    Job Description:

    A design-focused ASIC engineer will:


    • Perform logic design for the integration of cell libraries, functional units and sub-systems into SoC full chip designs


    • Perform Register Transfer Level (RTL) design and simulation for SoCs


    • Contribute to the development of multidimensional designs involving the layout of complex integrated circuits


    • Perform all aspects of the SoC design flow from high-level design synthesis to place and route, timing and power to create a design database that is ready for manufacturing.


    • Analyze equipment to establish operation infrastructure, conduct experimental tests, and evaluates results.


    • May also review vendor capability to support development

    Qualifications

    We are looking for enthusiastic individuals with strong problem-solving abilities, excellent communication and a desire to learn. Technically, a solid foundation of digital design (VHDL, Verilog) and object-oriented programming is desired.

    A verification-focused ASIC engineer will:


    • Ensure that the SoC meets the quality needs and requirements of our internal and external customers


    • Work closely with a wide variety of system disciplines (SoC designers, micro-architects, firmware, etc.) to understand the use cases and create a test and execution plan, ensuring that Company's products will be successful


    • Use industry-standard methodologies such as UVM, embedded C-based FW co-simulation, and formal property verification


    • Continuously investigate new tools and technologies

    Qualifications

    We are looking for enthusiastic individuals with strong problem-solving abilities, excellent communication and a desire to learn. Technically, a solid foundation of digital design (VHDL, Verilog) and object-oriented programming is desired.

    Minimum Qualifications for junior positions:


    • Strong debugging and problem-solving skills


    • Excellent written and verbal communication skills


    • Project-based teamwork experience


    • Fundamental digital logic design skills


    • Object-oriented programming experience


    • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent

    Preferred Qualifications for junior positions:


    • Linux experience


    • Languages: C, C++, Python, Java, Verilog (or VHDL), SystemVerilog


    • Verification methodologies: UVM, Formal Property Verification

    Minimum Qualifications for senior positions:


    • All minimum qualifications listed for junior positions


    • Minimum of 12 years of experience in ASIC/SoC design and/or verification environment


    • Very strong debugging and problem-solving skills supported by relevant experience


    • Digital logic design and implementation in advanced technology nodes


    • Working experience in UVM environment


    • Languages: C, C++, Python, Java, Verilog (or VHDL), SystemVerilog

    Preferred Qualifications for senior positions:


    • Leadership skills


    • Familiarity with formal verification methods


    • Familiarity with standard ASIC/SoC design flows including synthesis, DFT, STA, UPF, and ECO flows


    • Experience in low-power design techniques


    • Working knowledge of NVMe, PCIe, DDR and ARM standards


    • Familiarity with big box emulation platforms


    • Proven ability to architect and lead IP/SoC-level verification efforts

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