- Understand high-level ASIC requirements architecture and translate them into micro-architecture and high-level design.
- Lead the front-end ASIC design effort on complex ASIC sub-systems development from specifications to netlist hand-off to PnR.
- Support ASIC lead on project planning and management ASIC front-end developments.
- Support SOC integration and PnR team implementation to GDSII for the above.
- Design and implement RTL logic (mainly Verilog or System Verilog), run and debug block-level simulations, ASIC constraint development, synthesis and timing closure.
- Provide technical support to customers and lead them through complex technical issues.
- Minimum of an undergraduate degree in CS, EE or equivalent skills/experience.
- 12+ years of ASIC design and related experience.
- Experience with modern day ASIC development including RTL logic design, (physical) synthesis, STA, lint, LEC, and understanding of PnR.
- Proven experience with the duties and responsibilities listed above.
- Experience with complex asynchronous clock architectures and high-speed serial interfaces.
- Experience evaluating and integrating 3rd party IP.
- Experience or knowledge in some of the following: Multi-rate PCS, 10/25/40/100GbE, Transceivers, Packet Processing, OTN, Routers/Switches, Cellular, Mobile Devices, Video Processing, GPUs, AI Hardware Acceleration.
- Experience with industry standard interfaces e.g. Ethernet, OTN, SONET, PCIe, SPI, I2C, USB, AMBA, GPIO, SRIO, DDR/SDRAM, DMA, 4G, LTE, 5G, O-RAN, 3GPP, H.264.
- Experience in a lab environment, troubleshooting issues up to the system level.
- Track record as a self-starter, a team player and a leader.
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